VHDL UCF PARA MODULO CRONOMETRO UN MINUTO

# Para Spartan 3eSK y Pmod SSD
# Ing. <GutierrezMartinezJuan@Gmail.com>
# NOVIEMBRE 07 de 2016 - Probado on board
# Fuente de reloj
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;

#Pulsador de reset
NET "Reset" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "Pausa" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;


# slots
# ==== 6-pin header J1 ====
# These four connections are shared with the FX2 connector
NET "Dato_7Segmentos(0)" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; # a
NET "Dato_7Segmentos(1)" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; # b
NET "Dato_7Segmentos(2)" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; # c
NET "Dato_7Segmentos(3)" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; # d
# ==== 6-pin header J2 ====
# These four connections are shared with the FX2 connector
NET "Dato_7Segmentos(4)" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;# e
NET "Dato_7Segmentos(5)" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;# f
NET "Dato_7Segmentos(6)" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;# g
NET "Selector_Display"   LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;# selecciona display
# ==== 6-pin header J4 ====
# These four connections are shared with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;