VHDL TOP MODULE CRONOMETRO UN MINUTO

----------------------------------------------------------------------------------
-- Company:
-- Engineer: <GutierrezMartinezJuan@Gmail.com>
-- Create Date:    16:36:51 07/11/2016
-- Design Name:
-- Module Name:    Modulo_cronometro_Un_minuto - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e Satarter Board
-- Tool versions: ISE WEB PACK 14.6
-- Description: Conteo de un minuto y despliegue en Pmod SSD
-- Revision: 1
-- Revision 0.01 - File Created
-- Additional Comments: Probado on board NOV 18 de 2016 PMOD DSS S3eSK
-- SE ADICIONA PAUSA CONECTADA AL CONTADOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Modulo_cronometro_Un_minuto is
    Port ( Clk_50Mhz : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
 Pausa : in STD_LOGIC;
           Dato_7Segmentos : out  STD_LOGIC_VECTOR (6 downto 0);
           Selector_Display : out  STD_LOGIC);
end Modulo_cronometro_Un_minuto;

architecture Behavioral of Modulo_cronometro_Un_minuto is


COMPONENT Decodificador_BCD_7segmentos_KatodoComun
PORT(
Dato_BCD_in : IN std_logic_vector(3 downto 0);        
Dato_7Segmentos : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;


COMPONENT Divisor_frecuencia_1000Hz_2
PORT(
Clk_in_50MHz : IN std_logic;
Reset : IN std_logic;        
Clk_out_1000Hz : OUT std_logic
);
END COMPONENT;


COMPONENT Divisor_frecuencia_1Hz_2
PORT(
Clk_in_50MHz : IN std_logic;
Reset : IN std_logic;        
Clk_out_1Hz : OUT std_logic
);
END COMPONENT;

COMPONENT Multiplexor_2_1_4
PORT(
Unidades : IN std_logic_vector(3 downto 0);
Decenas : IN std_logic_vector(3 downto 0);
Selector_Digito : IN std_logic;        
Digito_BCD_out : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

COMPONENT ContadorBCD_00_59
PORT(
Clk_in : IN std_logic;
Reset : IN std_logic;
Pausa : IN std_logic;        
Unidades_Conteo_de0a9 : OUT std_logic_vector(3 downto 0);
Decenas_Conteo_de0a5 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

Signal aux1, aux5 : std_logic;
Signal aux2, aux3, aux4 : Std_logic_vector (3 downto 0);
begin

U1: Divisor_frecuencia_1Hz_2 PORT MAP(
Clk_in_50MHz => Clk_50Mhz,
Reset => Reset,
Clk_out_1Hz => aux1
);

U2: ContadorBCD_00_59 PORT MAP(
Clk_in => aux1,
Reset => Reset,
Unidades_Conteo_de0a9 => aux3,
Decenas_Conteo_de0a5 => aux2,
Pausa => Pausa
);

U3: Multiplexor_2_1_4 PORT MAP(
Unidades => aux3,
Decenas => aux2,
Selector_Digito => aux5,
Digito_BCD_out => aux4
);

U4: Divisor_frecuencia_1000Hz_2 PORT MAP(
Clk_in_50MHz => Clk_50Mhz,
Reset => Reset,
Clk_out_1000Hz => aux5
);

U6: Decodificador_BCD_7segmentos_KatodoComun PORT MAP(
Dato_BCD_in => Aux4,
Dato_7Segmentos => Dato_7Segmentos
);

Selector_Display <= aux5; -- ME AHORRA UN MODULO CONTADOR 00 01 00 01... CON ESTE FUNCIONA OK
end Behavioral;